blocks such as memory and IO have high material densities, which, along with neighboring circuits, have a significant impact on chemical mechanical polishing (CMP). Placement and routing (P&R) tools, however, are unaware of the topology or material density or line width structures inside the IP blocks, as only pin information is provided for chip designers and the P&R tools. Therefore, IP block material thickness, material density, topology, and the resulting CMP effects on a manufacturability of an SOC design, are only considered after tape-out. However, such CMP effects are becoming more prominent for 40 nm technology nodes and beyond. For instance, CMP effects due to accumulated topology caused by a high material density of metal structures in a wide area, may cause lithography and etch process issues. In addition, CMP effects may be caused by, for instance, a wide topology variation with a high standard of deviation from intra layer wide-width power lines. Thus, SOC designs or layouts may need to be modified after tape-out to address topology and CMP effects which were not considered during prior design steps. As such, manufacturers face significant challenges for reducing topology and CMP effects in various stages of design to improve a manufacturability of the SOC design.
FIG. 1 schematically illustrates an exemplary SOC design without a representation of an IP block topology before tape-out. As shown, the SOC design includes a placement 101 of adjacent IP blocks with a steep density increase, another placement 103 of adjacent IP blocks with a steep density increase, placement 105 of an IP block with a steep density increase, a placement 107 of an IP block requiring a thick copper (Cu) route, and a placement 109 of IP blocks having an inefficient floor plan. The placement 101 of adjacent IP blocks has a steep density increase because adjacent IP blocks include a low material density IP block 111, next to a high material density IP block 113. However, since blocks 111 and 113 are followed by a medium material density IP block 115, a more gradual density transition could be accomplished by placing the medium material density IP block 115 between the IP blocks 111 and 113. Similarly, the placement 103 of adjacent low and high material density IP blocks has a steep density transition. However, a wide width power preroute surrounding a high material density IP block 117 could make the density transition more gradual. In addition, the placement 105 of a high material density IP block, for example a memory, requires a steep density increase from lacking spacing to allow for a gradual density increase. Additionally, the placement 107 of a high material density IP block, for example a memory, requires a thick Cu route from being adjacent to an IP block 119. However, surrounding the placement 107 with a wide width power preroute could minimize the Cu thickness and increase a Cu thickness planarity of the SOC design. Further, the placement 109 of IP blocks is inefficient because the IP blocks may be orientated in a manner that uses less space in the layout. Additionally, a high material density block 119 may unnecessarily increase topology variation when another IP block capable of performing a similar function and having lower density is available. That is, SOC designs traditionally have a steep density increase and a selection of high material density IP blocks, resulting in an SOC design with significant topology variations and CMP effects.
A need therefore exists for a methodology enabling a representation of an IP block topology before tape-out of an SOC design that enables reduced topology and CMP effects, and the resulting designs.